HackerNews中文版

大家好！我构建了 SHDL（简单硬件描述语言），旨在通过剥离硬件描述，探究其最基本的原理。在 SHDL 中，没有算术运算符，没有隐式的位宽，也没有高级结构。你完全从逻辑门和导线开始，显式地构建一切，然后以分层的方式组合成更大的组件。其目标不是合成或性能，而是理解：当抽象被移除时，数字系统到底是什么样子的。 SHDL 配备了 PySHDL，这是一个 Python 接口，允许你加载电路，设置输入，运行仿真，并观察输出。在底层，SHDL 将电路编译成 C 语言以实现快速执行，但语言本身保持了刻意的小巧和透明。这并不是要取代 Verilog 或 VHDL。它的目标是： - 从基本原理学习数字逻辑 - 试验 HDL 和语言设计 - 教学或可视化复杂的硬件如何从简单的门电路中产生我特别希望收到关于以下方面的反馈： - 语言设计选择 - 哪些方面感觉不必要的限制，哪些方面具有教育价值 - 这种“反抽象”的 HDL 对你是否有用代码库：https://github.com/rafa-rrayes/SHDL Python 包：PySHDL 在 PyPI 上感谢阅读，我非常欢迎批评。

查看原文

Hi, everyone!I built SHDL (Simple Hardware Description Language) as an experiment in stripping hardware description down to its absolute fundamentals.In SHDL, there are no arithmetic operators, no implicit bit widths, and no high-level constructs. You build everything explicitly from logic gates and wires, and then compose larger components hierarchically. The goal is not synthesis or performance, but understanding: what digital systems actually look like when abstractions are removed.SHDL is accompanied by PySHDL, a Python interface that lets you load circuits, poke inputs, step the simulation, and observe outputs. Under the hood, SHDL compiles circuits to C for fast execution, but the language itself remains intentionally small and transparent.This is not meant to replace Verilog or VHDL. It’s aimed at:- learning digital logic from first principles- experimenting with HDL and language design- teaching or visualizing how complex hardware emerges from simple gatesI would especially appreciate feedback on:- the language design choices- what feels unnecessarily restrictive vs. educationally valuable- whether this kind of “anti-abstraction” HDL is useful to youRepo: https://github.com/rafa-rrayes/SHDLPython package: PySHDL on PyPIThanks for reading, and I’m very open to critique.

SHDL – 基于逻辑门构建的极简硬件描述语言